The present invention relates to a data input/output circuit operable in a multibit mode, suitable for a MOS dynamic RAM.
One method for shortening an access time of semiconductor DRAM ICs is to use a data input/output circuit operable in a multibit mode, e.g., a 4-bit (nibble) mode.
When a memory address is specified once, the input/output circuit can transfer 4-bit data serially at a high speed from a memory cell to a data output buffer or from a data output buffer to a memory cell.
Conventional data input/output circuits operating in the nibble mode are disclosed in, for example, "A 100 ns 256K DRAM with Page-Nibble Mode" by K. Shimotori et al., ISSCC DIGEST OF TECHNICAL PAPERS, P228-229; Feb., 1983, and "A sub 100 ns 256Kb DRAM" by T. Nakano et al., ISSCC DIGEST OF TECHNICAL PAPERS, P224-225; Feb., 1983.
The conventional data input/output circuits operate in a readout mode to transfer four bits of information from four bit lines to four data buses at a time, the four bits of information being amplified and latched respectively in four latch circuits Then, the four bits of information are transferred one bit by one bit serially from the latch circuits to a data output buffer After all data of the four data buses have been transmitted to a data output circuit, next 4-bit information is transferred to the data buses.
With the prior nibble-mode data input/output circuit, however, while data is being issued from one latch circuit, the other latch circuits are kept simply in a standby condition. Therefore, the operation efficiency of the data buses and the latch circuits is not high. In particular, where a plurality of such prior data input/output circuits are employed to issue pieces of serial information in a parallel manner to a plurality of data output terminals, there are required as many data buses, precharge circuits, and latch circuits as a multiple of the data output terminals, and the area taken up by the data input/output circuits is greatly increased. For these reasons, it has been difficult to fabricate high-capacity DRAM IC devices.
The conventional circuit arrangement has also been disadvantageous in that when multibit (four bits or more) data is to be accessed serially through the data output terminals, it is necessary to increase the number of data buses by the number of bits, with the result that the area occupied by the data buses makes it difficult to provide higher-density integration on semiconductor memory IC chips.